1. _ _ _ _ _ _ _ _ _ _ _ _ relieves the CPU from waiting for every I/O event, but many CPU cycles are still spent in transferring data<===>Interrupt-driver I/O
2. _ _ _ _ _ _ _ _ _ _ _ device is used to handle the complexities of disconnect / connect and read ahead in magnetic disks.<===>Disk controller
3. _ _ _ _ _ _ _ _ _ _ _ multithreading achieves the improvement in throughput at the cost of some overhead<===>simultaneous
4. _ _ _ _ _ _ _ _ _ _ automatically forces accesses to several disks.<===>striping
5. _ _ _ _ _ _ _ _ _ _ faults have declined due to a decreasing number of chips in systems, reduced power, and fewer connectors<===>Hardware
6. _ _ _ _ _ _ _ _ _ _ have the ability to work around failed nodes and switches<===>SANs
7. _ _ _ _ _ _ _ _ _ _ is the no of misses in cache divided by the total no of memory accesses to this cache<===>local miss rate
8. _ _ _ _ _ _ _ _ _ _ is the node where the memory location and the directory entry of an address reside.<===>home node
9. _ _ _ _ _ _ _ _ _ _ is used for congestion control in ATM<===>credit based
10. _ _ _ _ _ _ _ _ _ availability and _ _ _ _ _ _ _ _ _ extensibility make clusters attractive to service provides for the WWW.<===>High, incremental
11. _ _ _ _ _ _ _ _ _ is a common technique for reducing contention in shared resources including access to shared networks and buses<===>exponential back off
12. _ _ _ _ _ _ _ _ _ latency schemes sacrifice fault tolerance<===>low
13. _ _ _ _ _ _ _ _ _ optimization reduces misses by improved temporal locality<===>blocking
14. _ _ _ _ _ _ _ _ _ sends different streams simultaneously on the same fiber using different wavelengths of light.<===>WDM
15. _ _ _ _ _ _ _ _ _ tapes limit the speed at which the tapes can spin with out breaking or jamming.<===>helical scan
16. _ _ _ _ _ _ _ _ cache contains only blocks that are discarded from a cache because of a miss<===>victim
17. _ _ _ _ _ _ _ _ faults exist for a limited time and are not recurring<===>Transient
18. _ _ _ _ _ _ _ _ keeps the state of every block that may be cached<===>Directory
19. _ _ _ _ _ _ _ _ memory, divided physical memory into blocks and allocates them to different processes<===>virtual
20. _ _ _ _ _ _ _ _ misses decreases as associativity increases<===>collision
21. _ _ _ _ _ _ _ _ optimization improves cache performance without affecting the number of instructions executed<===>loop interchange
22. _ _ _ _ _ _ _ _ server has the goal that a node can fail or be upgraded without bringing down the whole machine.<===>Sun Fire 6800
23. _ _ _ _ _ _ _ _ tapes mean access to terabytes of information in tens of seconds.<===>near line
24. _ _ _ _ _ _ _ _ was deployed by cable television companies to deliver a higher rate over a few kilometers.<===>coaxial cable
25. _ _ _ _ _ _ _ actions introduce the possibility that the protocol can deadlock<===>non atomic
26. _ _ _ _ _ _ _ added to the cpu protection structure expand memory access protection from two levels to many more<===>rings
27. _ _ _ _ _ _ _ are used to send a value from the home node back to the requesting node<===>Data value reply
28. _ _ _ _ _ _ _ caches rely of write buffers<===>write back
29. _ _ _ _ _ _ _ conflict misses -are due to going from eight way associative to four- way associative<===>four way
30. _ _ _ _ _ _ _ field in the segment descriptor of IA-32 specifies the valid opera tions and protection levels for operations that use this segment<===>attributes
31. _ _ _ _ _ _ _ multithreading uses the insight that a dynamically scheduled processor already has many of the hardware mechanisms needed to support the integrated exploitation of TLP through multithreading .<===>simultaneous
32. _ _ _ _ _ _ _ occurs in paging<===>internal fragmentation
33. _ _ _ _ _ _ _ synchronization primitives returns the value of a memory location and automatically increments it<===>fetch-and-increment
34. _ _ _ _ _ _ followed open standards and have less stringent electrical requirements.<===>I/O buses
35. _ _ _ _ _ _ multithreading switches between threads on each instruction causing the execution of multiple threads to be interleaved<===>fine - grained
36. _ _ _ _ _ _ reconstruction speed implies _ _ _ _ _ _ _ __ application performance<===>increased, decreased
37. _ _ _ _ _ provides unique register identifiers , instructions from multiple threads can be mixed in the data path without confusing sources and destinations across the threads<===>Register renaming
38. _ _ _ _ transmits digital data as pulses of light<===>Fiber optics
39. A descriptor pointing to a _ _ _ _ _ _ _ _ segment is placed in the global descriptor table, while a descriptor for a __ _ _ _ _segment is placed in the local descriptor table.<===>shared, private
40. A gigabit per second LAN can fully occupy a _ _ _ _ _ _ _ _ GHZ CPU when running TCP/IP<===>0.8-1.0
41. A multi computer consisting of completely separate computers connected on a local area network are called _ _ _<===>Cluster
42. A quad processor running IIS/Windows 2000 is _ _ _ __ _ _ _ _ a dual processor running TUX/LINUX.<===>slower than
43. A SAN that tries to optimize based on shorter distance is _ _ _ _ _ _ _ _ _<===>Infiniband
44. A Sequential program in a cluster of N machines has _ __ _ _ _ _ _ _ _ _ _ _ the memory available compared to a sequential program in a shared memory multiprocessor.<===>1/N
45. Assume we have a computer where the clock per instruction (cpi) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores and these total 50 % of the instructions. If the miss penalty is 25 clock cycle and miss rate is 2 %,how much faster would the computer be if all the instructions were cache hits.<===>1.75
46. A system _ _ _ _ _ _ _ _ _ occurs when the actual behavior deviates from the specified behavior<===>failure
47. Achieving higher _ _ _ _ _ _ _ _ _ _ requires improvement in software quality and software fault tolerance.<===>Availability
48. Administering a cluster of N machines is close to the cost of administering<===>N independent machines
49. Alpha 21264 employs _ _ _ _ _ _ _ _ TLBs to reduce address translation time<===>2
50. An attempt to write a block in the _ _ _ _ _ _ _ state always generates a miss, even if the block is present in the cache , since the block must be made _ _ _ _ _ _ _ _ _ _ _ _<===>shared ,exclusive
51. Array density is measured as _ _ _ _ _ _ _ _ _ _ _ _ _<===>Tracks/inch on a disk surface*(bits/inch) on a track
52. Assume a disk subsystem with the following components and MTTF . 10 disks, each rated at 1,000,000 - hours MTTF . 1 SCSI controller, 200,000 - hours MTTF. . 1 power supply, 200,000 - hours MTTF . 1 FAN 200,000 - hours MTTF. . 1 SCSI cable, 1,000,000 - hours MTTF. Compute the MTTF of the system as a whole assuming that the age of the component is not important in probability of failure and that failures are independent<===>43,500 hours
53. Assuming that the components lifetimes are exponentially distributed and that failures are independent, compute . 1 power supply, 200,000 - hours MTTFthe failure rate of a disk subsystem with the following components and MTTF. 10 disks, each rated at 1,000,000 - hours MTTF . 1 SCSI controller, 200,000 - hours MTTF.<===>20/1,000,000
54. Astandard VME rack is _ _ _ _ _ _ _ _ _ inches wide and about _ _ _ _ _ _ _ _ feet tall, with a typical depth of _ _ _ _ _ _ _ _ _ _ inches respectively.<===>19,6,30
55. Au1000 includes about _ _ _ _ _ _ _ _ _ DMA channels and _ _ _ _ _ _ _ _ I/O device controllers on chip respectively.<===>10,20
56. Average memory access time= _ _ _ _ _ _ _ _ _<===>hit time+miss rate*miss penalty
57. Bridges operate at _ _ _ _ _ _ _ _ _ _ layer of the OSI model<===>Data link
58. By limiting the length to 100 meters,``Cat5" wiring can be used for _ _ _ _ _ _ _ _ _<===>1000M bits/sec
59. cache coherence is an accepted requirement in _ _ _ _ _multiprocessors<===>small-scale
60. Cache memory works on the _ _ _ _ _ _ _<===>Principle of locality
61. Clock rate of PCI is _ _ _ _ _ _ _ _ _ _<===>33 or 66MHz
62. Clusters are used for the _ _ _ _ _ _ _ _ computers, NUMA the _ _ _ _ _ _ _ _ computers<===>largest, smaller
63. Clusters are usually connected using the _ _ _ _ _ _ _ _ of the computer<===>I/O bus
64. Clusters gets _ _ _ _ _ _ _ _ performance by scaling.<===>high
65. Collaction rates are _ _ _ _ _ _ _ per unit as space requirements increases<===>much cheaper
66. Collaction Sites are designed assuming no more than _ __ _ watts per square foot.<===>100
67. consider a logical address space of eight pages of 1024 words each, mapped on to a physical memory of 32 frames . How many bits are there in the physical address<===>15
68. CPU time = _ _ _ _ _ _ _ _<===>(cpu execution clock cycles +memory stall clock cycles)*clock cycle time
69. Data cache performs slightly _ _ _ _ _ with SMT, while the l2 cache performs slightly _ _ _ _<===>worse ,better
70. Depending on the program, a _ _ _ _ _ _ _ _ victim cache might remove one- quarter of the misses in a 4KB direct mapped data cache<===>four entry
71. Directory requests need to _ _ _ _ _ _ _ _ _ the set shares and also _ _ _ _ _ _ _ the set to perform invalidations<===>read , update
72. Disk media failures on writes fall into which category of faults?<===>Permanent
73. Ethernet is codified as IEEE standard _ _ _ _ _ _ _ _ _ _<===>802.3
74. FC-AL can be connected in a loop with up to _ _ _ _ _ devices.<===>127
75. For every 100 NFS operations per second, the capacity must increase by _ _ _ _ _ _ _<===>1GB
76. For flash ,assume it takes 65ns to read 1 byte,1.5μs to write 1 byte and 5ms to erase 4KB.What are the times required to read and write a 64KB block to flash memory.<===>4.3,178.3
77. Hardware queuing locks implementation assumes a _ _ _ _ _ _ _ _ multiprocessor<===>directory-based
78. How many bus transactions are needed to have 10 processors lock and unlock the variable using a queuing lock that updates the lock on a miss?<===>3n-1
79. IBM RAID controller requires _ _ _ _ _ _ _ _ _ _ disk.<===>FC-AL
80. If an operation is done with out intervening operation then the operation are _ _ _ _ _ _ _ _<===>atomic
81. If multiprocessors are attempting to get the lock, each will generate the _ _ _ _ _ _<===>write
82. If the CPU uses a multi level cache with the _ _ _ _ _ property , then every entry in the Primary cache is required to be in the secondary cache<===>inclusion
83. If the memory hierarchies of the two computers are identical, the cpu with _ _ _ _ _ _ _ _clock rate has a _ _ number of clock cycles per miss.<===>higher, larger
84. If the number of failures of 58 desktop computers on a traditional LAN are 654 and that these failures are equally distributed among work stations, then what percentage of hours a user on a workstation can't get his work done.<===>0.13 %
85. If the OS uses 50,000 CPU instructions for a disk I/O. What is the maximum IOPS for CPU with 2500 MIPS?<===>50,000 IOPS
86. If the upper level memory is smaller than what is needed for a program and a significant percentage of the time is spend moving data between two levels in the hierarchy, the memory hierarchy is said to _ _ _ _ _ _ _ _<===>trash
87. In _ _ _ _ _ _ _ , the cpu and the memory is shared among several interactive uses at the same time, giving the illusion that all users have their own computers<===>timesharing
88. In _ _ _ _ _ _ _ _ _ _ _ _ , portions of the machines address space are assigned to I/O devices.<===>Memory mapped I/O
89. In a directory protocol in which state no processor has a copy of the cache block?<===>uncached
90. In a failure-intolerant LAN if thetotal intervals and intervals of no failures are 8974 and 8605 respectively, then what percentages of hours a user can`t get his work done<===>4.1 %
91. In alpha memory management, _ _ _ _ _ _ _ _ _ is reserved for the operating system kernel, has uniform protection for the whole space, and does not use memory management<===>kseg
92. In alpha memory management, which protection field allows the kernel to read the data within the page<===>kernel read enable
93. In Performance-tuned organization the disk utilization is _ _ _ _ _ _ _ _ _ _ _<===>80 %
94. In the _ _ _ _ _ _ _ _ case the interleaving of threads eliminate fully empty slots<===>super scalar
95. In which design of I/O system shows the folly of 100 % utilization<===>Response times of the naive cost-preformance design & evaluation
96. In which of the multiprocessors communication of data is done by explicitly passing messages among the processors?<===>message passing multiprocessors
97. In which state exactly one processor has a copy of the cache block and it has written the block , so the memory copy is out of date<===>exclusive
98. Level 3 unshielded twisted pairs was good enough for _ _ _ _ _ _ _ _ _ Ethernet<===>10M bits/sec
99. Linux reconstructs _ _ _ _ _ _ _ _ _ and Solaris reconstructs _ _ _ _ _ _ _ _ _ _<===>slowly, quickly
100. Low cost VCRS and camcorders make us of _ _ _ _ _ _ _ _ _ _ _ _ _ _ tapes<===>helical scan
101. Mean-time until data loss (MTDL) increase with _ _ _ __ _ _ _ disk reliability, and _ _ _ _ _ _ _ _ _ _ MTTR.<===>Increased, reduced
102. Memory bus has _ _ _ _ bandwidth and _ _ _ latency.<===>higher, lower
103. Memory buses provide _ _ _ _ _ _ _ bandwidth and _ _ _ _ _ _ latency than I/O buses<===>Higher,lower
104. Memory stall cycles= _ _ _ _ _ _ _ _ _ _<===>number. of misses* miss penalty
105. Miss penalty is measured in _ _ _ _ _ _ _ _<===>cpu clock cycles for a miss
106. Multiple writes to the same word with no intervening reads require _ _ _ _ _ _ _ write broadcast in an update protocol<===>multiple
107. N devices generally have _ _ _ _ _ _ _ _ _ _ the reliability of a single device<===>1/N
108. Non redundant disk array is often called _ _ _ _ _ _ _ __ _ _ _ _<===>Raid 0
109. Optimization in directory protocols often add complexity by _ _ _ _ _ _ _ _ _ possibility of deadlock and by _ _ _ _ _ __ the types of messages that must be handled.<===>increasing ,increasing
110. Replication _ _ _ _ _ _ _ _ latency of access and _ _ _ _ __ _ _ contention for a read shared data item<===>reduces , reduces
111. Rewritable DVD drives cost _ _ _ _ _ _ times as much as DVD-ROM drives<===>10
112. Routers are _ _ _ _ _ _ _ _ _ _ _ than Bridges<===>slower
113. Segment registers in the IA - 32 contains and index to a virtual memory data structure called a _ _ _ _ _ _ _ table<===>descriptor
114. Simulation results have shown that sharing everything is key to maximizing _ _ _ _ _ _ _ _<===>simultaneous MT
115. Small SMP's with _ _ _ _ _ _ _ _ processors has much better cost-performance than clusters<===>2-4
116. Smaller computers are generally _ _ _ _ and _ _ _ _ _ _ _ for a given function compared to the larger computers.<===>Cheaper , faster
117. SMT exploits _ _ _ _ _ _ _ _ _ _ _ parallelism on a multiple-issue superscalar and hence it is included in _ _ _ _ _ _ _ _ _ processors targeted at server markets<===>thread level, high-end
118. Software failures occur _ _ _ _ _ _ _ _ _ than Hardware failures<===>much more frequently
119. Split-transaction bus has _ _ _ _ _ _ _ _ _ _ band width, but it usually has _ _ _ _ _ _ _ _ _ latency than a bus that is held during the complete transaction<===>Higher, higher
120. Storage device used for embedded applications is _ _ _ _ _ _ _ _ _<===>flash memory
121. Succesful standards include _ _ _ _ _ _ _ _ cost and stability<===>Low
122. Suppose there are 10 processors on a bus that each they to execute a barrier Simultaneously. Determine the number of bus transactions required for all 10 Processors to reach the barrier, be released from the barrier and exit the barrier<===>204
123. Suppose you have 25 magnetic tapes, each containing 40GB.Assume that you have enough tape readers to keep any network busy. How long will it take to transmit the data over a distance of 1 Km using cat5 twisted pair wires at 100M bits/sec.<===>22.8 hrs
124. Synchronization problems are quite acute in _ _ _ _ _ _ __ _ microprocessors<===>large- scale
125. Th advertised average seek time is 5 ms, the transfer rate is 40MB/Sec, it rotates at 10,000 RPM and the controller overhead is 0.1ms. Assume the disk is idle so that there is no queuing delay. What is the average time to read or write a 512 byte sector for a disk?<===>8.11
126. The _ _ _ _ _ _ _ the CPI execution, the _ _ _ _ _ _ _ the relative impact of the fixed no of cache miss clock cycles.<===>lower, higher
127. The alpha memory management uses a _ _ _ _ _ _ _ page table to map the address space to keep the size reasonable<===>TLB
128. The behavior of reads and writes to the same memory location is defined as _ _ _<===>coherence
129. The civilian programs are the _ _ _ _ _ _ trusted and hence, have the _ _ _ _ _ _ limited range of accesses<===>most , least
130. The communication system must have mechanisms for _ _ _ _ _ _ _ of a message in case of failure<===>Retransmission
131. The cost of building basic synchronization primitives will be too _ _ _ _ _ _ _ _ _ and will _ __ _ _ _ _ _ as the processor count increases<===>high,increase
132. The database cost is primarily a _ _ _ _ _ _ _ _ _ _ function of the number of processors.<===>linear
133. The diameter of multimode fiber is _ _ _ _ _ _ _ _ _ _ _<===>62.5 microns
134. The disk surface is divided into concentric circle, designated _ _ _ _ _ _ _ _ _ _ _<===>Tracks
135. The distributed parity organization is _ _ _ _ _ _ _ _ _ _<===>Raid 5
136. The latency of the 21264 data cache is _ _ _ _ _ _ clock cycles<===>3
137. The loss of signal strength as it passes through a medium, called _ _ _ _ _ _ , limits the length of the fiber<===>Attenuation
138. The processor configuration for the evaluation of an SMT extension starts with an aggressive superscalar that has capacity of existing superscalar processors in 2001.roughly _ _ _ _ _ _ _ _ the<===>double
139. The processors with the sole copy of a cache block is normally called the _ _ _ _ of the cache block.<===>owner
140. The size of the page table is _ _ _ _ _ _ _ the page size<===>inversely proportional to
141. The storage overhead of RAID 6 is _ _ _ _ _ _ _ _ _ _ __ that of RAID 5<===>twice
142. The uniprocessor clusters costs _ _ _ _ _ _ times the two-way SMP option, and the 8 way SMP cluster costs _ _ _ _ _ _ _ _ _ _ times the two way SMP.<===>1.6, 1.1
143. The very first access to a block cannot be in the cache, so the block must the brought into the cache. These are called __ _ _ _ misses<===>compulsory
144. The work-load is gradually _ _ _ _ _ _ _ _ _ _ until the server software is saturated with hits and the response time _ _ _ Significantly<===>increases, decreases
145. To reduce the address translation time , computers use a cache dedicated to these address translations called a _ _ _ _ _<===>TLB
146. TPC-C cluster scale by a factor of _ _ _ _ _ _ _ _ in price or processors while maintaining respectable cost-performance.<===>8
147. Transaction processing is concerned with _ _ _ _ _ _ _ _<===>I/O rate
148. Transferring _ _ _ _ _ _ _ _ _ pages to or from secondary storage, possibly over a network, is more efficient than transferring _ _ _ _ _ _ _ _ pages<===>larger, smaller
149. Vector architectures are the largest class of processors of __ _ _ _ _ type<===>SIMD
150. Virtual memory system include a _ _ _ _ _ _ _ _ bit, since the cost of an unnecessary access to the next lower level is so high<===>dirty
151. What are the local and global miss rates of second level cache if in 1000 memory references there are 40 misses in the first level cache and 20 misses in the second level cache<===>50 % and 2 %
152. what fraction of the original computation can be sequential to achieve a speed up of 80 with 100 processors?<===>0.25
153. What is the bench mark used for evaluating the performance of WWW Servers<===>SPECWEB
154. What is the disk access latency for performance and availability tuned organization<===>41ms
155. What is the interconnection network used in cray T3E multiprocessors?<===>2-way 3D torus
156. What is the maximum number of processes in sun star fire servers ?<===>64
157. What is the miss penalty of L1 cache<===>hit time L2 + miss rate L2 *miss penalty L2
158. What is the number of bus transactions required for all n processors to acquire a lock on a variable simultaneously, assuming they are all spinning when the lock is released at time 0.<===>n2 +2n
159. What is the performance metric of complex query OLTP bench mark<===>new order transactions per minute
160. What is the remote request cost for an application running on a 32- processor Multiprocessors, which has a 400ns time to handle reference to a remote memory. The processors clock rate is 1GHz<===>400 cycles
161. What is the response time of an I/O system with a single disk, if it gets on average 64 I/O requests per second and the average disk service time in 7.8 ms.<===>15.6ms
162. What is the size of L2 Cache in xseries370?<===>1024kB
163. What is the size of the page table, given a 32 bit virtual address, 4 KB pages and 4 bytes per page table entry<===>4MB
164. What is the size of the smallest packet on the Ethernet<===>64 bytes
165. What is the typical remote memory access time of HPV series?<===>1000
166. What is the utilization of seek time per disk, if the time of average seek in 5s with 100 IOPS<===>50 %
167. What message type and contents are to be transmitted from the local cache to the home director when a processor P has a read miss at address A request data and make P a read sharer<===>Read miss P,A
168. when the cpu finds a requested data item in cache, it is called a _ _ _ _ _ _ _<===>cache hit
169. Which among the following is a simplex media<===>fiber optics
170. Which among the following is connection oriented<===>ATM
171. Which among the following is not a cache optimization technique<===>reducing the miss penalty or miss rate via serialism
172. Which among the following is not a fault classification in VAX systems<===>design fault
173. Which among the following operate at the network layer of OSI model<===>routers
174. Which design cluster example includes the cost of software, the cost of space, some maintenance costs and operator costs.<===>Cost of cluster options that in more realistic
175. Which directory request sets the shares to the identity of the new owner and the state of the block remains exclusive.<===>write miss
176. Which is the best I/O technique to send large messages?<===>DMA
177. Which is the probable architecture for on-chip multiprocessors<===>SMP
178. Which mechanism allows the same program to run in any location in physical memory<===>Relocation
179. Which miss penalty reduction technique ignores the cpu, concentrating on the interface between the cache and main memory<===>multilevel caches
180. Which miss penalty technique combines writes to sequential words into a single block to create a more efficient transfer of memory<===>merging write buffer
181. Which miss penalty technique is based on the observation that the cpu normally needs just one word of the block at a time<===>critical word first and early restart
182. Which miss rate reduction technique is popular in off chip caches<===>larger caches
183. Which miss rate reduction technique reduces miss rates without any hardware changes<===>compiler optimizations
184. Which of the following is a false statement regarding distributed shared memory multiprocessors.<===>It increases the latency for accesses to the local memory
185. Which of the following is a false statement regarding the I/O processor<===>parallelism they enable is very high
186. Which of the following is a serial I/O bus often used in embedded computers.<===>SPI
187. Which of the following is not a characteristic of TPC bench mark.<===>The benchmark results are not audited
188. Which of the following is not true regarding SAN<===>SANs appreciate dropping packets during congestion is critical for SANS
189. Which of the following statement is false about finegrained multithreading<===>it fastens the execution of the individual threads
190. Which of the following statement is false regarding writeback cache<===>they are not preferable in multiprocessors.
191. Which of the following statement is false<===>Cost of the bus is high
192. Which of the following statement is true about single mode fiber<===>More expensive
193. Which of the following statement is true regarding I/O bus.<===>Have a wide range in the data bandwidth of the devices connected to them
194. Which of the following statements is false about queuing locks<===>They are used to reduce the performance of barrier operation
195. Which of the following statements is not true about blocking<===>blocking algorithms operate on entire rows or columns of an array
196. Which of the following violates rule of thumb<===>No disk string should be utilized less than 40 %
197. Which option for a bus among the following leads to high performance.<===>Synchronous
198. With virtual memory, the cpu produces _ _ _ _ _ _ _ _ addresses<===>virtual
199. Write - back caches generate _ _ _ _ _ _ requirements for memory bandwidth , and slightly __ _ _ _ _ _ in complexity<===>lower, increase
200. Write buffers hold the update value of a location needed on a _ _ _ _ _ _ _ _<===>read miss
2. _ _ _ _ _ _ _ _ _ _ _ device is used to handle the complexities of disconnect / connect and read ahead in magnetic disks.<===>Disk controller
3. _ _ _ _ _ _ _ _ _ _ _ multithreading achieves the improvement in throughput at the cost of some overhead<===>simultaneous
4. _ _ _ _ _ _ _ _ _ _ automatically forces accesses to several disks.<===>striping
5. _ _ _ _ _ _ _ _ _ _ faults have declined due to a decreasing number of chips in systems, reduced power, and fewer connectors<===>Hardware
6. _ _ _ _ _ _ _ _ _ _ have the ability to work around failed nodes and switches<===>SANs
7. _ _ _ _ _ _ _ _ _ _ is the no of misses in cache divided by the total no of memory accesses to this cache<===>local miss rate
8. _ _ _ _ _ _ _ _ _ _ is the node where the memory location and the directory entry of an address reside.<===>home node
9. _ _ _ _ _ _ _ _ _ _ is used for congestion control in ATM<===>credit based
10. _ _ _ _ _ _ _ _ _ availability and _ _ _ _ _ _ _ _ _ extensibility make clusters attractive to service provides for the WWW.<===>High, incremental
11. _ _ _ _ _ _ _ _ _ is a common technique for reducing contention in shared resources including access to shared networks and buses<===>exponential back off
12. _ _ _ _ _ _ _ _ _ latency schemes sacrifice fault tolerance<===>low
13. _ _ _ _ _ _ _ _ _ optimization reduces misses by improved temporal locality<===>blocking
14. _ _ _ _ _ _ _ _ _ sends different streams simultaneously on the same fiber using different wavelengths of light.<===>WDM
15. _ _ _ _ _ _ _ _ _ tapes limit the speed at which the tapes can spin with out breaking or jamming.<===>helical scan
16. _ _ _ _ _ _ _ _ cache contains only blocks that are discarded from a cache because of a miss<===>victim
17. _ _ _ _ _ _ _ _ faults exist for a limited time and are not recurring<===>Transient
18. _ _ _ _ _ _ _ _ keeps the state of every block that may be cached<===>Directory
19. _ _ _ _ _ _ _ _ memory, divided physical memory into blocks and allocates them to different processes<===>virtual
20. _ _ _ _ _ _ _ _ misses decreases as associativity increases<===>collision
21. _ _ _ _ _ _ _ _ optimization improves cache performance without affecting the number of instructions executed<===>loop interchange
22. _ _ _ _ _ _ _ _ server has the goal that a node can fail or be upgraded without bringing down the whole machine.<===>Sun Fire 6800
23. _ _ _ _ _ _ _ _ tapes mean access to terabytes of information in tens of seconds.<===>near line
24. _ _ _ _ _ _ _ _ was deployed by cable television companies to deliver a higher rate over a few kilometers.<===>coaxial cable
25. _ _ _ _ _ _ _ actions introduce the possibility that the protocol can deadlock<===>non atomic
26. _ _ _ _ _ _ _ added to the cpu protection structure expand memory access protection from two levels to many more<===>rings
27. _ _ _ _ _ _ _ are used to send a value from the home node back to the requesting node<===>Data value reply
28. _ _ _ _ _ _ _ caches rely of write buffers<===>write back
29. _ _ _ _ _ _ _ conflict misses -are due to going from eight way associative to four- way associative<===>four way
30. _ _ _ _ _ _ _ field in the segment descriptor of IA-32 specifies the valid opera tions and protection levels for operations that use this segment<===>attributes
31. _ _ _ _ _ _ _ multithreading uses the insight that a dynamically scheduled processor already has many of the hardware mechanisms needed to support the integrated exploitation of TLP through multithreading .<===>simultaneous
32. _ _ _ _ _ _ _ occurs in paging<===>internal fragmentation
33. _ _ _ _ _ _ _ synchronization primitives returns the value of a memory location and automatically increments it<===>fetch-and-increment
34. _ _ _ _ _ _ followed open standards and have less stringent electrical requirements.<===>I/O buses
35. _ _ _ _ _ _ multithreading switches between threads on each instruction causing the execution of multiple threads to be interleaved<===>fine - grained
36. _ _ _ _ _ _ reconstruction speed implies _ _ _ _ _ _ _ __ application performance<===>increased, decreased
37. _ _ _ _ _ provides unique register identifiers , instructions from multiple threads can be mixed in the data path without confusing sources and destinations across the threads<===>Register renaming
38. _ _ _ _ transmits digital data as pulses of light<===>Fiber optics
39. A descriptor pointing to a _ _ _ _ _ _ _ _ segment is placed in the global descriptor table, while a descriptor for a __ _ _ _ _segment is placed in the local descriptor table.<===>shared, private
40. A gigabit per second LAN can fully occupy a _ _ _ _ _ _ _ _ GHZ CPU when running TCP/IP<===>0.8-1.0
41. A multi computer consisting of completely separate computers connected on a local area network are called _ _ _<===>Cluster
42. A quad processor running IIS/Windows 2000 is _ _ _ __ _ _ _ _ a dual processor running TUX/LINUX.<===>slower than
43. A SAN that tries to optimize based on shorter distance is _ _ _ _ _ _ _ _ _<===>Infiniband
44. A Sequential program in a cluster of N machines has _ __ _ _ _ _ _ _ _ _ _ _ the memory available compared to a sequential program in a shared memory multiprocessor.<===>1/N
45. Assume we have a computer where the clock per instruction (cpi) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores and these total 50 % of the instructions. If the miss penalty is 25 clock cycle and miss rate is 2 %,how much faster would the computer be if all the instructions were cache hits.<===>1.75
46. A system _ _ _ _ _ _ _ _ _ occurs when the actual behavior deviates from the specified behavior<===>failure
47. Achieving higher _ _ _ _ _ _ _ _ _ _ requires improvement in software quality and software fault tolerance.<===>Availability
48. Administering a cluster of N machines is close to the cost of administering<===>N independent machines
49. Alpha 21264 employs _ _ _ _ _ _ _ _ TLBs to reduce address translation time<===>2
50. An attempt to write a block in the _ _ _ _ _ _ _ state always generates a miss, even if the block is present in the cache , since the block must be made _ _ _ _ _ _ _ _ _ _ _ _<===>shared ,exclusive
51. Array density is measured as _ _ _ _ _ _ _ _ _ _ _ _ _<===>Tracks/inch on a disk surface*(bits/inch) on a track
52. Assume a disk subsystem with the following components and MTTF . 10 disks, each rated at 1,000,000 - hours MTTF . 1 SCSI controller, 200,000 - hours MTTF. . 1 power supply, 200,000 - hours MTTF . 1 FAN 200,000 - hours MTTF. . 1 SCSI cable, 1,000,000 - hours MTTF. Compute the MTTF of the system as a whole assuming that the age of the component is not important in probability of failure and that failures are independent<===>43,500 hours
53. Assuming that the components lifetimes are exponentially distributed and that failures are independent, compute . 1 power supply, 200,000 - hours MTTFthe failure rate of a disk subsystem with the following components and MTTF. 10 disks, each rated at 1,000,000 - hours MTTF . 1 SCSI controller, 200,000 - hours MTTF.<===>20/1,000,000
54. Astandard VME rack is _ _ _ _ _ _ _ _ _ inches wide and about _ _ _ _ _ _ _ _ feet tall, with a typical depth of _ _ _ _ _ _ _ _ _ _ inches respectively.<===>19,6,30
55. Au1000 includes about _ _ _ _ _ _ _ _ _ DMA channels and _ _ _ _ _ _ _ _ I/O device controllers on chip respectively.<===>10,20
56. Average memory access time= _ _ _ _ _ _ _ _ _<===>hit time+miss rate*miss penalty
57. Bridges operate at _ _ _ _ _ _ _ _ _ _ layer of the OSI model<===>Data link
58. By limiting the length to 100 meters,``Cat5" wiring can be used for _ _ _ _ _ _ _ _ _<===>1000M bits/sec
59. cache coherence is an accepted requirement in _ _ _ _ _multiprocessors<===>small-scale
60. Cache memory works on the _ _ _ _ _ _ _<===>Principle of locality
61. Clock rate of PCI is _ _ _ _ _ _ _ _ _ _<===>33 or 66MHz
62. Clusters are used for the _ _ _ _ _ _ _ _ computers, NUMA the _ _ _ _ _ _ _ _ computers<===>largest, smaller
63. Clusters are usually connected using the _ _ _ _ _ _ _ _ of the computer<===>I/O bus
64. Clusters gets _ _ _ _ _ _ _ _ performance by scaling.<===>high
65. Collaction rates are _ _ _ _ _ _ _ per unit as space requirements increases<===>much cheaper
66. Collaction Sites are designed assuming no more than _ __ _ watts per square foot.<===>100
67. consider a logical address space of eight pages of 1024 words each, mapped on to a physical memory of 32 frames . How many bits are there in the physical address<===>15
68. CPU time = _ _ _ _ _ _ _ _<===>(cpu execution clock cycles +memory stall clock cycles)*clock cycle time
69. Data cache performs slightly _ _ _ _ _ with SMT, while the l2 cache performs slightly _ _ _ _<===>worse ,better
70. Depending on the program, a _ _ _ _ _ _ _ _ victim cache might remove one- quarter of the misses in a 4KB direct mapped data cache<===>four entry
71. Directory requests need to _ _ _ _ _ _ _ _ _ the set shares and also _ _ _ _ _ _ _ the set to perform invalidations<===>read , update
72. Disk media failures on writes fall into which category of faults?<===>Permanent
73. Ethernet is codified as IEEE standard _ _ _ _ _ _ _ _ _ _<===>802.3
74. FC-AL can be connected in a loop with up to _ _ _ _ _ devices.<===>127
75. For every 100 NFS operations per second, the capacity must increase by _ _ _ _ _ _ _<===>1GB
76. For flash ,assume it takes 65ns to read 1 byte,1.5μs to write 1 byte and 5ms to erase 4KB.What are the times required to read and write a 64KB block to flash memory.<===>4.3,178.3
77. Hardware queuing locks implementation assumes a _ _ _ _ _ _ _ _ multiprocessor<===>directory-based
78. How many bus transactions are needed to have 10 processors lock and unlock the variable using a queuing lock that updates the lock on a miss?<===>3n-1
79. IBM RAID controller requires _ _ _ _ _ _ _ _ _ _ disk.<===>FC-AL
80. If an operation is done with out intervening operation then the operation are _ _ _ _ _ _ _ _<===>atomic
81. If multiprocessors are attempting to get the lock, each will generate the _ _ _ _ _ _<===>write
82. If the CPU uses a multi level cache with the _ _ _ _ _ property , then every entry in the Primary cache is required to be in the secondary cache<===>inclusion
83. If the memory hierarchies of the two computers are identical, the cpu with _ _ _ _ _ _ _ _clock rate has a _ _ number of clock cycles per miss.<===>higher, larger
84. If the number of failures of 58 desktop computers on a traditional LAN are 654 and that these failures are equally distributed among work stations, then what percentage of hours a user on a workstation can't get his work done.<===>0.13 %
85. If the OS uses 50,000 CPU instructions for a disk I/O. What is the maximum IOPS for CPU with 2500 MIPS?<===>50,000 IOPS
86. If the upper level memory is smaller than what is needed for a program and a significant percentage of the time is spend moving data between two levels in the hierarchy, the memory hierarchy is said to _ _ _ _ _ _ _ _<===>trash
87. In _ _ _ _ _ _ _ , the cpu and the memory is shared among several interactive uses at the same time, giving the illusion that all users have their own computers<===>timesharing
88. In _ _ _ _ _ _ _ _ _ _ _ _ , portions of the machines address space are assigned to I/O devices.<===>Memory mapped I/O
89. In a directory protocol in which state no processor has a copy of the cache block?<===>uncached
90. In a failure-intolerant LAN if thetotal intervals and intervals of no failures are 8974 and 8605 respectively, then what percentages of hours a user can`t get his work done<===>4.1 %
91. In alpha memory management, _ _ _ _ _ _ _ _ _ is reserved for the operating system kernel, has uniform protection for the whole space, and does not use memory management<===>kseg
92. In alpha memory management, which protection field allows the kernel to read the data within the page<===>kernel read enable
93. In Performance-tuned organization the disk utilization is _ _ _ _ _ _ _ _ _ _ _<===>80 %
94. In the _ _ _ _ _ _ _ _ case the interleaving of threads eliminate fully empty slots<===>super scalar
95. In which design of I/O system shows the folly of 100 % utilization<===>Response times of the naive cost-preformance design & evaluation
96. In which of the multiprocessors communication of data is done by explicitly passing messages among the processors?<===>message passing multiprocessors
97. In which state exactly one processor has a copy of the cache block and it has written the block , so the memory copy is out of date<===>exclusive
98. Level 3 unshielded twisted pairs was good enough for _ _ _ _ _ _ _ _ _ Ethernet<===>10M bits/sec
99. Linux reconstructs _ _ _ _ _ _ _ _ _ and Solaris reconstructs _ _ _ _ _ _ _ _ _ _<===>slowly, quickly
100. Low cost VCRS and camcorders make us of _ _ _ _ _ _ _ _ _ _ _ _ _ _ tapes<===>helical scan
101. Mean-time until data loss (MTDL) increase with _ _ _ __ _ _ _ disk reliability, and _ _ _ _ _ _ _ _ _ _ MTTR.<===>Increased, reduced
102. Memory bus has _ _ _ _ bandwidth and _ _ _ latency.<===>higher, lower
103. Memory buses provide _ _ _ _ _ _ _ bandwidth and _ _ _ _ _ _ latency than I/O buses<===>Higher,lower
104. Memory stall cycles= _ _ _ _ _ _ _ _ _ _<===>number. of misses* miss penalty
105. Miss penalty is measured in _ _ _ _ _ _ _ _<===>cpu clock cycles for a miss
106. Multiple writes to the same word with no intervening reads require _ _ _ _ _ _ _ write broadcast in an update protocol<===>multiple
107. N devices generally have _ _ _ _ _ _ _ _ _ _ the reliability of a single device<===>1/N
108. Non redundant disk array is often called _ _ _ _ _ _ _ __ _ _ _ _<===>Raid 0
109. Optimization in directory protocols often add complexity by _ _ _ _ _ _ _ _ _ possibility of deadlock and by _ _ _ _ _ __ the types of messages that must be handled.<===>increasing ,increasing
110. Replication _ _ _ _ _ _ _ _ latency of access and _ _ _ _ __ _ _ contention for a read shared data item<===>reduces , reduces
111. Rewritable DVD drives cost _ _ _ _ _ _ times as much as DVD-ROM drives<===>10
112. Routers are _ _ _ _ _ _ _ _ _ _ _ than Bridges<===>slower
113. Segment registers in the IA - 32 contains and index to a virtual memory data structure called a _ _ _ _ _ _ _ table<===>descriptor
114. Simulation results have shown that sharing everything is key to maximizing _ _ _ _ _ _ _ _<===>simultaneous MT
115. Small SMP's with _ _ _ _ _ _ _ _ processors has much better cost-performance than clusters<===>2-4
116. Smaller computers are generally _ _ _ _ and _ _ _ _ _ _ _ for a given function compared to the larger computers.<===>Cheaper , faster
117. SMT exploits _ _ _ _ _ _ _ _ _ _ _ parallelism on a multiple-issue superscalar and hence it is included in _ _ _ _ _ _ _ _ _ processors targeted at server markets<===>thread level, high-end
118. Software failures occur _ _ _ _ _ _ _ _ _ than Hardware failures<===>much more frequently
119. Split-transaction bus has _ _ _ _ _ _ _ _ _ _ band width, but it usually has _ _ _ _ _ _ _ _ _ latency than a bus that is held during the complete transaction<===>Higher, higher
120. Storage device used for embedded applications is _ _ _ _ _ _ _ _ _<===>flash memory
121. Succesful standards include _ _ _ _ _ _ _ _ cost and stability<===>Low
122. Suppose there are 10 processors on a bus that each they to execute a barrier Simultaneously. Determine the number of bus transactions required for all 10 Processors to reach the barrier, be released from the barrier and exit the barrier<===>204
123. Suppose you have 25 magnetic tapes, each containing 40GB.Assume that you have enough tape readers to keep any network busy. How long will it take to transmit the data over a distance of 1 Km using cat5 twisted pair wires at 100M bits/sec.<===>22.8 hrs
124. Synchronization problems are quite acute in _ _ _ _ _ _ __ _ microprocessors<===>large- scale
125. Th advertised average seek time is 5 ms, the transfer rate is 40MB/Sec, it rotates at 10,000 RPM and the controller overhead is 0.1ms. Assume the disk is idle so that there is no queuing delay. What is the average time to read or write a 512 byte sector for a disk?<===>8.11
126. The _ _ _ _ _ _ _ the CPI execution, the _ _ _ _ _ _ _ the relative impact of the fixed no of cache miss clock cycles.<===>lower, higher
127. The alpha memory management uses a _ _ _ _ _ _ _ page table to map the address space to keep the size reasonable<===>TLB
128. The behavior of reads and writes to the same memory location is defined as _ _ _<===>coherence
129. The civilian programs are the _ _ _ _ _ _ trusted and hence, have the _ _ _ _ _ _ limited range of accesses<===>most , least
130. The communication system must have mechanisms for _ _ _ _ _ _ _ of a message in case of failure<===>Retransmission
131. The cost of building basic synchronization primitives will be too _ _ _ _ _ _ _ _ _ and will _ __ _ _ _ _ _ as the processor count increases<===>high,increase
132. The database cost is primarily a _ _ _ _ _ _ _ _ _ _ function of the number of processors.<===>linear
133. The diameter of multimode fiber is _ _ _ _ _ _ _ _ _ _ _<===>62.5 microns
134. The disk surface is divided into concentric circle, designated _ _ _ _ _ _ _ _ _ _ _<===>Tracks
135. The distributed parity organization is _ _ _ _ _ _ _ _ _ _<===>Raid 5
136. The latency of the 21264 data cache is _ _ _ _ _ _ clock cycles<===>3
137. The loss of signal strength as it passes through a medium, called _ _ _ _ _ _ , limits the length of the fiber<===>Attenuation
138. The processor configuration for the evaluation of an SMT extension starts with an aggressive superscalar that has capacity of existing superscalar processors in 2001.roughly _ _ _ _ _ _ _ _ the<===>double
139. The processors with the sole copy of a cache block is normally called the _ _ _ _ of the cache block.<===>owner
140. The size of the page table is _ _ _ _ _ _ _ the page size<===>inversely proportional to
141. The storage overhead of RAID 6 is _ _ _ _ _ _ _ _ _ _ __ that of RAID 5<===>twice
142. The uniprocessor clusters costs _ _ _ _ _ _ times the two-way SMP option, and the 8 way SMP cluster costs _ _ _ _ _ _ _ _ _ _ times the two way SMP.<===>1.6, 1.1
143. The very first access to a block cannot be in the cache, so the block must the brought into the cache. These are called __ _ _ _ misses<===>compulsory
144. The work-load is gradually _ _ _ _ _ _ _ _ _ _ until the server software is saturated with hits and the response time _ _ _ Significantly<===>increases, decreases
145. To reduce the address translation time , computers use a cache dedicated to these address translations called a _ _ _ _ _<===>TLB
146. TPC-C cluster scale by a factor of _ _ _ _ _ _ _ _ in price or processors while maintaining respectable cost-performance.<===>8
147. Transaction processing is concerned with _ _ _ _ _ _ _ _<===>I/O rate
148. Transferring _ _ _ _ _ _ _ _ _ pages to or from secondary storage, possibly over a network, is more efficient than transferring _ _ _ _ _ _ _ _ pages<===>larger, smaller
149. Vector architectures are the largest class of processors of __ _ _ _ _ type<===>SIMD
150. Virtual memory system include a _ _ _ _ _ _ _ _ bit, since the cost of an unnecessary access to the next lower level is so high<===>dirty
151. What are the local and global miss rates of second level cache if in 1000 memory references there are 40 misses in the first level cache and 20 misses in the second level cache<===>50 % and 2 %
152. what fraction of the original computation can be sequential to achieve a speed up of 80 with 100 processors?<===>0.25
153. What is the bench mark used for evaluating the performance of WWW Servers<===>SPECWEB
154. What is the disk access latency for performance and availability tuned organization<===>41ms
155. What is the interconnection network used in cray T3E multiprocessors?<===>2-way 3D torus
156. What is the maximum number of processes in sun star fire servers ?<===>64
157. What is the miss penalty of L1 cache<===>hit time L2 + miss rate L2 *miss penalty L2
158. What is the number of bus transactions required for all n processors to acquire a lock on a variable simultaneously, assuming they are all spinning when the lock is released at time 0.<===>n2 +2n
159. What is the performance metric of complex query OLTP bench mark<===>new order transactions per minute
160. What is the remote request cost for an application running on a 32- processor Multiprocessors, which has a 400ns time to handle reference to a remote memory. The processors clock rate is 1GHz<===>400 cycles
161. What is the response time of an I/O system with a single disk, if it gets on average 64 I/O requests per second and the average disk service time in 7.8 ms.<===>15.6ms
162. What is the size of L2 Cache in xseries370?<===>1024kB
163. What is the size of the page table, given a 32 bit virtual address, 4 KB pages and 4 bytes per page table entry<===>4MB
164. What is the size of the smallest packet on the Ethernet<===>64 bytes
165. What is the typical remote memory access time of HPV series?<===>1000
166. What is the utilization of seek time per disk, if the time of average seek in 5s with 100 IOPS<===>50 %
167. What message type and contents are to be transmitted from the local cache to the home director when a processor P has a read miss at address A request data and make P a read sharer<===>Read miss P,A
168. when the cpu finds a requested data item in cache, it is called a _ _ _ _ _ _ _<===>cache hit
169. Which among the following is a simplex media<===>fiber optics
170. Which among the following is connection oriented<===>ATM
171. Which among the following is not a cache optimization technique<===>reducing the miss penalty or miss rate via serialism
172. Which among the following is not a fault classification in VAX systems<===>design fault
173. Which among the following operate at the network layer of OSI model<===>routers
174. Which design cluster example includes the cost of software, the cost of space, some maintenance costs and operator costs.<===>Cost of cluster options that in more realistic
175. Which directory request sets the shares to the identity of the new owner and the state of the block remains exclusive.<===>write miss
176. Which is the best I/O technique to send large messages?<===>DMA
177. Which is the probable architecture for on-chip multiprocessors<===>SMP
178. Which mechanism allows the same program to run in any location in physical memory<===>Relocation
179. Which miss penalty reduction technique ignores the cpu, concentrating on the interface between the cache and main memory<===>multilevel caches
180. Which miss penalty technique combines writes to sequential words into a single block to create a more efficient transfer of memory<===>merging write buffer
181. Which miss penalty technique is based on the observation that the cpu normally needs just one word of the block at a time<===>critical word first and early restart
182. Which miss rate reduction technique is popular in off chip caches<===>larger caches
183. Which miss rate reduction technique reduces miss rates without any hardware changes<===>compiler optimizations
184. Which of the following is a false statement regarding distributed shared memory multiprocessors.<===>It increases the latency for accesses to the local memory
185. Which of the following is a false statement regarding the I/O processor<===>parallelism they enable is very high
186. Which of the following is a serial I/O bus often used in embedded computers.<===>SPI
187. Which of the following is not a characteristic of TPC bench mark.<===>The benchmark results are not audited
188. Which of the following is not true regarding SAN<===>SANs appreciate dropping packets during congestion is critical for SANS
189. Which of the following statement is false about finegrained multithreading<===>it fastens the execution of the individual threads
190. Which of the following statement is false regarding writeback cache<===>they are not preferable in multiprocessors.
191. Which of the following statement is false<===>Cost of the bus is high
192. Which of the following statement is true about single mode fiber<===>More expensive
193. Which of the following statement is true regarding I/O bus.<===>Have a wide range in the data bandwidth of the devices connected to them
194. Which of the following statements is false about queuing locks<===>They are used to reduce the performance of barrier operation
195. Which of the following statements is not true about blocking<===>blocking algorithms operate on entire rows or columns of an array
196. Which of the following violates rule of thumb<===>No disk string should be utilized less than 40 %
197. Which option for a bus among the following leads to high performance.<===>Synchronous
198. With virtual memory, the cpu produces _ _ _ _ _ _ _ _ addresses<===>virtual
199. Write - back caches generate _ _ _ _ _ _ requirements for memory bandwidth , and slightly __ _ _ _ _ _ in complexity<===>lower, increase
200. Write buffers hold the update value of a location needed on a _ _ _ _ _ _ _ _<===>read miss
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